That’s like saying a bus driver’s job is to turn a steering wheel.

That’s a good analogy, I will use that.

I don’t think this will work well and others already explained why, but thanks for using this community to pitch your idea. We should have more of these discussions here rather than CEO news and tech gossip.

I don’t realistically expect such ban to happen. I started banning everyone who posts about Musk instead, my feed got a lot cleaner.

It is easier to implement ALU, memory and interpreter in Verilog and run the code with that at that point.

You can have 3 perpendicular lines if you use 3rd dimension too.

I would love some uvm content as well.

Nice and rare to see a fellow SV user. Did you come across to any relevant communities for digital design and verification, asic or fpga?